Low-k and ultra low-k dielectric materials used in semiconductor nodes typically have very low tensile strength, which makes them susceptible to cracking due to conventional packaging induced forces. Two such conventional packaging techniques are flip-chipping and wire bonding.
Flip-chipping is a process in which a semiconductor chip has solder bumps attached to one side of the chip and then the chip is “flipped over” and attached to a substrate having solder pads. The chips with the solder bumps are sometimes referred to as “flip chips.” This type of packaging technique places the chip layers at the bond pads under high stresses due to thermal stresses encountered during assembly and reliability testing.
Another type of packaging technique is wire-bonding where thin wires are used to connect the bond pads on the chip to the pads on the substrate. These wires have long lead lengths that suffer from poor electrical performance, especially at high speeds. In addition, this technique also puts the chips layers at the bond pads under high stress due to forces encountered during the wire bonding process.